发明名称 |
Memory transistor array utilizing insulated word lines as gate electrodes |
摘要 |
A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.
|
申请公布号 |
US7023061(B2) |
申请公布日期 |
2006.04.04 |
申请号 |
US20050072505 |
申请日期 |
2005.03.07 |
申请人 |
NOMOTO KAZUMASA;KOBAYASHI TOSHIO;NAKAMURA AKIHIRO;FUJIWARA ICHIRO;TERANO TOSHIO |
发明人 |
NOMOTO KAZUMASA;KOBAYASHI TOSHIO;NAKAMURA AKIHIRO;FUJIWARA ICHIRO;TERANO TOSHIO |
分类号 |
H01L29/76;H01L21/28;H01L21/8246;H01L27/115 |
主分类号 |
H01L29/76 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|