发明名称 |
Built-in self test circuitry for process monitor circuit for rapidchip and ASIC devices |
摘要 |
A test circuitry approach which addresses the shortcoming associated with current process monitor circuitry. The approach provides a means of testing that can be employed in association with any and all tester platforms. On-chip built-in self test (BIST) circuitry is added to the design that analyzes the 10-bit value captured from the counter, and indicates to the ATE via a single pin at a single test vector location whether or not the device has passed its test limits. An alternative solution is to use the digital capture circuitry on a mixed-signal tester to capture the non-deterministic digital word generated by the process monitor circuitry, and then test that result against the desired test limits.
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申请公布号 |
US2006069968(A1) |
申请公布日期 |
2006.03.30 |
申请号 |
US20040954906 |
申请日期 |
2004.09.30 |
申请人 |
GEARHARDT KEVIN;GREEB ANITA |
发明人 |
GEARHARDT KEVIN;GREEB ANITA |
分类号 |
G01R31/28 |
主分类号 |
G01R31/28 |
代理机构 |
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主权项 |
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地址 |
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