| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an erroneous writing prevention circuit reducing occurrence of erroneous writing with a simple configuration. <P>SOLUTION: An OR gate 3 allows passage of a writing signal/WR outputted from a CPU in time of an open state, and does not allow the passage in time of a closed state. A permission/non-permission register 6 comprising NAND gates 4, 5 outputs a gate control signal/WRC controlling opening/closing of the OR gate 3. An OR gate 8 generates a set signal/S on the basis of a signal outputted when the CPU accesses a non-volatile memory 2, and outputs it to the permission/non-permission register 6. When the CPU outputs a signal for indicating another device, an OR gate 9 and inverters 10, 11 generate a reset signal/R, and output it to the permission/non-permission register 6. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
