A DAC architecture is described. The architecture is specifically adapted to provided an analog voltage output based on a digital input word. The architecture includes a resistor ladder configuration sub-divisible into a first component, adapted to convert a lower part of the input word, and a second component adapted to convert an upper part of the input word. The DAC is calibrated such that the first component can be used to tune the output of the second component on selection of specific segment from the second component.
申请公布号
WO2006032592(A1)
申请公布日期
2006.03.30
申请号
WO2005EP54141
申请日期
2005.08.23
申请人
ANALOG DEVICES, INC.;KIRBY, PATRICK C.;LYDEN, COLIN G.;VINEREANU, TUDOR M.
发明人
KIRBY, PATRICK C.;LYDEN, COLIN G.;VINEREANU, TUDOR M.