| 摘要 |
A merged structure SRAM cell is provided that includes a first transistor and a second transistor. The second transistor gate forms a load resistor for the first transistor and the first transistor gate forms a load resistor for the second transistor. Also provided is a method of reading a memory cell that comprises applying a potential difference (V<SUB>DIFF</SUB>) to a selected memory cell by providing a column line potential (V<SUB>C</SUB>) and a row line potential (V<SUB>R</SUB>). According to this method, V<SUB>DIFF </SUB>is increased by an increment less than a transistor threshold voltage (V<SUB>T</SUB>). It is then determined whether the increased V<SUB>DIFF </SUB>results in a current flow on the column line for the selected memory cell. Also provided is a method of writing a memory cell that comprises applying V<SUB>DIFF </SUB>and increasing V<SUB>DIFF </SUB>by an increment more than V<SUB>T </SUB>to set the selected memory cell to a one state.
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