| 摘要 |
<p>The present invention proposes a methodology implementable in form of a hardware or software module for generating a pseudo random number. The pseudo random number corresponds to a pseudo random sequence of bits, which form the pseudo random number. A plurality of m polynomials is provided. The polynomials are derived from an original polynomial, which defines a feedback function of a linear feedback shift register capable for generating the pseudo random number. The polynomials are functions of n bits, which serve as initial bits and seed bits, respectively. Then, the polynomials are applied on the initial bits for generating the pseudo random number, which comprises at least m bits resulting from the m polynomials. Due to the fact that the polynomials are independent from each other, i.e. the initial bits serve as input values to the polynomials, the polynomials can be applied substantially simultaneously or in any other sequence.</p> |
