| 摘要 |
PROBLEM TO BE SOLVED: To widen the pull-in range of a clock in a digital PLL circuit (widening a range). SOLUTION: A reproduction RF signal reproduced from an optical magnetic disk 11 by an optical head 13 and obtained via an RF amplifier 14 is sent to the digital PLL circuit 15 and a sample value synchronized with the phase of a clock component in the reproduction RF signal is obtained by the digital PLL circuit 15. The operating clock of the digital PLL circuit 15 is supplied from an operating clock generating PLL circuit 21. In accordance with data reproduction speed obtained from an ADIP signal from the RF amplifier 14 by a data reproduction speed detecting circuit 26, the frequency of the operating clock outputted from the operating clock generation PLL circuit 21 is variably controlled. COPYRIGHT: (C)2006,JPO&NCIPI
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