发明名称 METHOD FOR LAYOUT OF SEMICONDUCTOR INTEGRATED CIRCUIT, PROGRAM FOR LAYOUT OF SEMICONDUCTOR INTEGRATED CIRCUIT, AND SYSTEM FOR LAYOUT OF SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To shorten the design period of a multi-powered semiconductor integrated circuit by automating the connection of a fixed input level signal terminal and a power line. SOLUTION: In the execution of placement and routing for a layout object circuit using circuit connection information 10 and power supply information 12, the following are executed: a first step (S11) of identifying a power terminal corresponding to a signal terminal designated at a fixed input level in the circuit connection information according to terminal correspondence information 14, a second step (S12) of identifying a supply voltage corresponding to the power terminal identified in the first step according to the power supply information, and a third step (S13) of routing a power line of the supply voltage identified in the second step to the fixed input level signal terminal to connect them. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006085576(A) 申请公布日期 2006.03.30
申请号 JP20040271674 申请日期 2004.09.17
申请人 FUJITSU LTD 发明人 MORITA HIROTAKA;FUKAZAWA SHINJI
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
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