| 摘要 |
A method for fabricating transistor structures for DRAM semiconductor components includes forming gate conductor structures in a cell array of a DRAM semiconductor component and covering the structures with a spacer liner. The gate conductor structures lie on a silicon semiconductor substrate. A masked spacer etch produces a spacer mask with horizontal sections and vertical spacer structures from the spacer liner for aligning implantation steps and for self-aligned formation of silicide structures at the surface of the semiconductor substrate. A CB contact implantation step is provided prior to the filling of trenches between the gate conductor structures with dielectric silicate glass fillings, and this obviates the need for an isolated high-temperature activation anneal for the CB contact implantation as well as reducing the thermal stresses on regions of the semiconductor substrate which have already been doped. A reflow heating step for partially melting the silicate glass is controlled as a final furnace anneal for annealing lattice defects in the semiconductor substrate. The contact resistance of a bit contact structure is lowered, while at the same time the thermal stresses are reduced.
|
