发明名称 Multiple-input, single-exit delay line architecture
摘要 A delay line includes a delay chain consisting of series-connected NAND gate delay stages with a delayed output signal extracted from the final delay stage. Tap decode gates are preferably used to "inject" the input signal to be delayed into the delay chain using one input of the NAND gate delay stage, referred to as an "injection point." The desired delay is achieved by selecting an injection point relative to the final delay stage, or exit point, of the delay chain. Selection of an injection point is provided by the binary decode of a tap address that activates the injection NAND gate delay stage, allowing the injected signal to propagate from the activated injection point to the exit point of the delay chain.
申请公布号 US2006066372(A1) 申请公布日期 2006.03.30
申请号 US20040950608 申请日期 2004.09.27
申请人 COLLINS HANSEL A;LINSTADT JOHN E 发明人 COLLINS HANSEL A.;LINSTADT JOHN E.
分类号 H03H11/26 主分类号 H03H11/26
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