SYSTEM, LOGIC, APPARATUS, AND METHOD FOR VERIFYING DESIGN

摘要

PROBLEM TO BE SOLVED: To provide a technic for verifying a design and a product in a high degree of level in verification. SOLUTION: The technic realizes test and verification of the design and the product in high level abstraction using a message chart with an intensive expression function to solve a problem mentioned above. The method to verify the design in the high level, comprises the steps of: receiving an input data for the design; generating the message chart describing the relationship of messages, which is communicated between a plurality of processes; determining at least one scenario comprising a sequence of the messages specified by the message chart from the message chart; generating an operative state machine so that at least transmit and receive a portion of the message chart specified by the converted message in accordance with the scenario can be transmitted and received; and testing an embodiment of the design by using the state machine. COPYRIGHT: (C)2006,JPO&NCIPI