发明名称 |
Memory controller for processor having multiple programmable units |
摘要 |
A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor-also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.
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申请公布号 |
US2006069882(A1) |
申请公布日期 |
2006.03.30 |
申请号 |
US20050232566 |
申请日期 |
2005.09.21 |
申请人 |
INTEL CORPORATION, A DELAWARE CORPORATION |
发明人 |
WHEELER WILLIAM R.;BURRES BRADLEY;ADILETTA MATTHEW J.;WOLRICH GILBERT |
分类号 |
G06F13/00;G06F13/16 |
主分类号 |
G06F13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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