DELAY LOCK LOOP CIRCUIT, PHASE LOCK LOOP CIRCUIT, TIMING GENERATOR, SEMICONDUCTOR TESTER AND SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

It is possible to reduce the lock-up time, extend the lock range without increasing the number of bits of a counter, and quickly return to a lock target upon deviation from the lock target. There are provided a plurality of phase comparators (11a, 11b), counters (12a, 12b), and DA converters (13a, 13b). Resolution per unit bit of the DA converters (13a, 13b) is differentiated. An adder element (14) adds the delay times indicated by delay time signals outputted from the DA converters (13a, 13b), and a BIAS (15) converts the sum of delay times into the delay time of delay elements in an delay element group (16) and supplies it to an output signal.