| 摘要 |
The present invention is related to a method for singulating at least one chip from a stack of layers, said stack comprising a front end of line (FEOL) (5) upon a substrate layer (1), said substrate layer having a first and a second surface, said FEOL (5) being positioned on top of said first surface, and a back end of line (BEOL) (6) on top of said FEOL, said method comprising the steps of : etching singulating trenches through said BEOL (6), through said FEOL (5) and at least partially through said substrate layer (1) of said stack, depositing a passivation layer on said stack provided with singulating trenches, whereby also said trenches' sidewalls are at least partially passivated, releasing said chip from said stack of layers. The present invention is related to a method for singulating a chip from a stack of layers, said stack comprising a front end of line (FEOL) (5) upon a substrate layer (1), said substrate layer having a first and second surface, said FEOL (5) being positioned on top of said first surface, and a back end line (BEOL) (6) on top of said FEOL, said method comprising the steps of: etching singulating trenches through said BEOL (6), through said FEOL (5) and at least partially through said substrate layer (1) of said stack, depositing a passivation layer on said stack provided with singulating trenches, whereby also said trenches' sidewalls are at least partially passivated, reducing the thickness of said substrate layer from said second surface onwards until said chip is released from said stack. |
