发明名称 Multilayer metallization
摘要 Multiple metallization layers in a partially fabricated integrated circuit are formed in a single process step. As a place-holder for the later-deposited metallization layers, sacrificial material is deposited in the integrated circuit at desired locations at various fabrication levels over a substrate. The sacrificial material is then removed to form a contiguous open volume spanning multiple fabrication levels. A conductor is then deposited in the open volume to form multiple metallization layers in a single step.
申请公布号 US7018917(B2) 申请公布日期 2006.03.28
申请号 US20030719277 申请日期 2003.11.20
申请人 ASM INTERNATIONAL N.V. 发明人 ELERS KAI-ERIK
分类号 H01L21/4763;H01L21/288;H01L21/768;H01L23/48 主分类号 H01L21/4763
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