| 摘要 |
An arithmetic device able to optimize the logic level, able to prevent an increase in the component data, able to prevent the area efficiency as an integrated operation efficiency, and circuit, achieving an improvement in the achieving a reduction power consumption, provided with a first selection device for selecting coefficient inputs C 0 I to CkI in accordance with a control signal ASEL, a second selection device for selecting data inputs D 0 I to DmI in accordance with a control signal BSEL, a third selection device for selecting cascade inputs P 0 to Pn-2 in accordance with a control signal CSEL, an ALU for receiving as input the output signal of the first to third selection devices and performing a logic operation in accordance with instructions of the control signals ALUMD etc., a MAC for receiving as input the output signals of the first to third selection devices and performing operation in accordance with instructions of
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