Alternative video sync detector

摘要

A circuit for generating video synchronization timing signals includes a negative peak detector (FIG. 5 ) for following variations of a composite video signal (FIG. 1 ), rather than clamping the most negative voltage of the composite video signal. The negative peak detector provides a voltage level V_TIP representative of the voltage at the synchronization tip of the composite video signal. A sample and hold circuit ( 700,702,704 ) is used to add an offset V_SLICE to V_TIP, V_SLICE being a voltage level of the breezeway, color burst, or back porch segments of the composite video signal, or a combination of these segments. The sample and hold circuit generates a signal V_REF, and is connected by a resistor divider ( 708,710 ) to the negative peak detector to form the signal V_TIP+V_SLICE provided to an amplifier ( 606 ) functioning as a comparator. The signal V_SLICE+V_TIP is compared in comparator ( 606 ) with the composite video signal to provide an overall circuit output. Buffering is provided at the input of the negative peak detector by amplifier ( 600 ) to reduce any DC offset from the diode of the negative peak detector. To prevent amplifier DC offset error voltages from affecting the perceived V_SLICE level, an amplifier ( 800 ) can be connected in a first position T_TIP as part of a negative peak detector to store V_TIP on a capacitor, in a second position T_H as part of a sample and hold circuit to store V_REF on a capacitor, and in a third position T_COMP to compare V_SLICE+V_TIP measured from the capacitors with the composite video signal to generate the overall circuit output.