发明名称 CLOCK AND DATA RECOVERY CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a clock and data recovery circuit which follows a frequency and a phase variation of serial data and has an excellent jitter strength characteristic in a clock and data recovery circuit. <P>SOLUTION: A feedback controller 107 composing a clock and data recovery circuit monitors a following rate of an extraction clock for a frequency and a phase variation of serial data, and performs a feedback control to an integrator 102 momently and adaptively, thereby increasing the following rate of the extraction clock and realizing an improvement of a jitter strength characteristic. <P>COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006080991(A) 申请公布日期 2006.03.23
申请号 JP20040264232 申请日期 2004.09.10
申请人 NEC ELECTRONICS CORP 发明人 TAKEUCHI MASAHIRO
分类号 H03L7/093;H03L7/06;H03L7/107;H03L7/113;H04L7/033 主分类号 H03L7/093
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