SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To reduce a phase comparison error in a phase comparing circuit in a phase adjusting circuit.

SOLUTION: A phase adjusting circuit (130) is arranged between a first line (L1) being orthogonal to a line (201) connecting a clock input part (190) and a data input part (112) and passing through the clock input part and a second line (L2) being parallel to the first line and passing through the clock input part side in the data input part. Since distance from the clock input part to a regular clock input circuit in the phase adjusting circuit and distance from a data input/output part to a replica clock input circuit in the phase adjusting circuit can be made almost equal by arranging the phase adjusting circuit between the first line and the second line, length of a wire from the clock input part to the regular clock input circuit and that of a wire from the data input/output part to the replica clock input circuit are made almost equal.

COPYRIGHT: (C)2006,JPO&NCIPI