Integrated semiconductor memory, has compression unit to compress comparison data to compressed error date that is selectable over external data connection, and switching unit is switched between comparator and compression circuits

摘要

The memory has an error analysis circuit (20) to execute a target data comparison between target and test data. The circuit produces a test date of the test data in comparator circuits with comparison date. The comparison date are compressed in a compression unit (25) to a compressed error date, which is selectable over an external data connection. A switching unit is switched between the comparator circuits and the circuit (25). An independent claim is also included for a method for testing an integrated semiconductor memory.