发明名称 SIGNAL SPLITTER
摘要 <p>A controllable-gain circuit (TI, Rt, TS1, .., TS4) provides a first and a second pair of complementary gain-controlled signals (Ip1, Ip3; Ip2, Ip4) in response to an input signal (RFI). In each pair, one gain-controlled signal (Ipl, Ip2) is the input signal amplified with a gain G comprised in a range between a minimum gain Gmin and a maximum gain Gmax. The other gain-controlled signal (Ip3, Ip4) is the input signal amplified with complementary gain Gmax-G. A fixed-gain output circuit (Rfg, Nfg) makes a weighed sum (Ipl *Rfg + Ip3*Rfg) of one and the other gain-controlled signal in the first pair of complementary gain-controlled signals. The respective weighing factors for one and the other gain-controlled signal are substantially similar (Rfg). A controllable-gain output circuit (Rlg, Rhg, Nlg, Nhg) makes a weighed sum (Ip2*Rlg + Ip4*(Rlg+Rhg)) of one and the other gain­controlled signal in the second pair of complementary gain-controlled signals. The respective weighing factors for one and the other gain-controlled signal are substantially different (Rlg, Rlg+Rhg).</p>
申请公布号 WO2006030358(A1) 申请公布日期 2006.03.23
申请号 WO2005IB52942 申请日期 2005.09.08
申请人 KONINKLIJKE PHILIPS ELECTRONICS N.V.;KERVAON, THIBAULT, P., P.;AMIOT, SEBASTIEN 发明人 KERVAON, THIBAULT, P., P.;AMIOT, SEBASTIEN
分类号 H03G1/00 主分类号 H03G1/00
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