发明名称 A METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR GENERATING AND VERIFYING ISOLATION LOGIC MODULES IN DESIGN OF INTEGRATED CIRCUITS
摘要 A method, system and computer program product for generating and verifying the correctness of isolation logic modules in design of integrated circuits (ICs). The method disclosed generates an isolation logic module for each power domain specified by a user, instantiates the generated module in a pre-determined wakeup domain, and then simulates shutdown conditions to ensure the correctness of the generated isolation logic module. The isolation logic is generated based on user-defined voltage constraints.
申请公布号 US2006064293(A1) 申请公布日期 2006.03.23
申请号 US20040711493 申请日期 2004.09.21
申请人 ATRENTA, INC. 发明人 KAPOOR BHANU;BAGCHI DEBABRATA;CHURIWALA SANJAY
分类号 G06F17/50 主分类号 G06F17/50
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