发明名称 |
SEMICONDUCTOR MEMORY DEVICE AND POWER SIGNAL LAYOUT METHOD OF THE SAME |
摘要 |
The semiconductor memory has pad power lines (PVSS1,PVSS1'',PVDD1,PVDD1'') arranged below the lower pads in the pad structures (PVDD,PVSS), in a direction crossing the pad structures to interconnect the pad structures transmitting the same level of electrical power. The sub-pad power lines are arranged in a direction perpendicular to the pad power lines. An independent claim is also included for method of power line arrangement in semiconductor memory. |
申请公布号 |
KR20060026352(A) |
申请公布日期 |
2006.03.23 |
申请号 |
KR20040075233 |
申请日期 |
2004.09.20 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
KIM, SUNG HOON;CHO, YOUNG CHUL;PARK, KWANG IL;JANG, SEONG JIN |
分类号 |
G11C5/06;G11C5/14 |
主分类号 |
G11C5/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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