Field effect transistor comprises wire channels electrically connecting source and drain regions and arranged in two columns and at least two rows

摘要

A field effect transistor (FET) comprises semiconductor substrate; source and drain regions (42) formed on substrate; wire channels (12e) electrically connecting the source and drain regions and arranged in two columns and at least two rows; and gate dielectric layer surrounding each of the wire channels and a gate electrode surrounding the gate dielectric layer and each of the wire channels. An independent claim is also included for a method of fabricating a field effect transistor comprising: (a) forming a channel forming preparation layer on the semiconductor substrate, the channel forming preparation layer including a first sacrificial layer, first channel layer, second sacrificial layer and second channel layer sequentially stacked on the substrate; (b) forming a hard mask layer on the channel forming preparation layer; (c) patterning the hard mask layer and the channel forming preparation layer to define an active region of the substrate; (d) patterning the hard mask layer to narrow the hard mask layer exposing an edge portion of an upper surface of the channel forming preparation layer; (e) forming a first dielectric layer on the substrate to cover the narrowed hard mask layer and the channel forming preparation layer, then planarizing the first dielectric layer to expose the narrowed hard mask layer; (f) patterning the first dielectric layer and a portion of the narrowed hard mask layer to remove a portion of the narrowed hard mask layer to form a dummy gate pattern and exposing a portion of the channel forming preparation layer; (g) selectively etching the exposed portion of the channel forming preparation layer adjacent to the dummy gate pattern to expose the substrate; (h) selectively growing an epitaxial layer on the exposed substrate to form source and drain patterns (40) adjacent to the channel forming preparation layer; (i) forming a second dielectric layer on the substrate including the dummy gate and the source and drain patterns and then planarizing the second dielectric layer to expose the dummy gate pattern; (j) selectively etching the remaining hard mask layer to remove the remaining hard mask layer so exposing a portion of the channel forming preparation layer and then etching the exposed portion of the channel forming preparation layer to expose the substrate; (k) removing the second dielectric layer and an upper portion of the first dielectric layer to expose sidewalls of the channel forming preparation layer remaining on the substrate; (l) selectively etching the channel forming preparation layer to remove the two sacrificial layers to form wire channels from the two channel layers; (m) forming a gate dielectric layer on the substrate to surround each of the wire channels; and (n) forming a gate electrode on the gate dielectric layer to form a gate surrounding each of the wire channels.