发明名称 |
Method of floorplanning and cell placement for integrated circuit chip architecture with internal I/O ring |
摘要 |
A method and computer program are disclosed for floorplanning and cell placement of an integrated circuit architecture that include steps of: (a) receiving as input a design for an integrated circuit architecture that includes a plurality of modules and an internal I/O ring; (b) creating a floorplan to define an area for placing module cells for each module in the plurality of modules wherein for each module that overlaps the internal I/O ring, an area of intersection between the area defined for placing the module cells and an area bounded by a side of the internal I/O ring for which the area of intersection is least is a global minimum for the plurality of modules; and (c) generating as output the floorplan for the integrated circuit architecture.
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申请公布号 |
US2006064662(A1) |
申请公布日期 |
2006.03.23 |
申请号 |
US20040947618 |
申请日期 |
2004.09.22 |
申请人 |
TETELBAUM ALEXANDER;MBOUOMBOUO BENJAMIN |
发明人 |
TETELBAUM ALEXANDER;MBOUOMBOUO BENJAMIN |
分类号 |
G06F17/50;G06F9/45 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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