| 摘要 |
PROBLEM TO BE SOLVED: To update chip information by altering patterns of wires and via holes in the same layer as a layer where patterns of wires and via holes are altered for logic correction, characteristic improvement, etc. SOLUTION: The 1st wiring 21p of a 1st wire layer is regarded as a start end 20, which is connected to a ground potential VSS. The 1st wiring 21p and the 2nd wiring 22p of a 2nd wire layer are connected by a 1st connection 31p. The 2nd wiring 22p and the 3rd wiring 23p of a 3rd wire layer are connected by a 2nd connection 32p. A 4th wiring 24p connecting with the 3rd wiring 23p and the 5th wiring 25p of the 2nd wire layer are connected by a 3rd connection 33p. The 5th wiring 25p and the 6th wiring 26p of the 1st wire layer are connected by a 4th connection 34p. Conduction paths which are in a mountain shape like this are connected to form a continuous conduction path 100 connected from the start end 20 to an output end 39. COPYRIGHT: (C)2006,JPO&NCIPI
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