发明名称 |
Multi-bit stacked-type non-volatile memory and manufacture method thereof |
摘要 |
The present invention discloses a multi-bit stacked-type non-volatile memory having a spacer-shaped floating gate and a manufacturing method thereof. The manufacturing method includes forming a patterned dielectric layer containing arsenic on a semiconductor substrate, wherein the patterned dielectric layer defines an opening as an active area. A dielectric spacer is formed on a side wall of the patterned dielectric layer and a gate dielectric layer is formed on the semiconductor substrate. A source/drain region is formed by thermal driving method making arsenic diffusion from the patterned dielectric layer into the semiconductor substrate. A spacer-shaped floating gate is formed on the side wall of the dielectric spacer and the gate dielectric layer. An interlayer dielectric layer is formed on the spacer-shaped floating gate. A control gate is formed on the interlayer dielectric layer and fills the opening of the active area.
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申请公布号 |
US2006063339(A1) |
申请公布日期 |
2006.03.23 |
申请号 |
US20050269671 |
申请日期 |
2005.11.09 |
申请人 |
NANYA TECHNOLOGY CORPORATION |
发明人 |
HSIAO CHING-NAN;LIN CHI-HUI;CHUANG YING-CHENG |
分类号 |
H01L21/331;H01L21/28;H01L21/336;H01L21/82;H01L21/8222;H01L21/8242;H01L27/115;H01L29/788 |
主分类号 |
H01L21/331 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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