发明名称 Processor arrangement having a stack memeory
摘要 A processor 10 including a control unit 12, a program ROM 14 in communication with the control unit 12 for loading program instructions, and a stack memory 22 for storing data during execution of a program, wherein the stack memory 22 is adapted to handle data on a first in last out basis. Such a stack memory 22 can be used as a primary data storage mechanism in the processor 10 and can be used to replace the internal registers and conventional RAM of the prior processor.
申请公布号 GB2418272(A) 申请公布日期 2006.03.22
申请号 GB20040020686 申请日期 2004.09.17
申请人 MARCONI COMMUNICATIONS LTD 发明人 GRAHAM BUTLER
分类号 G06F9/30;G06F7/78;G06F15/78 主分类号 G06F9/30
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