发明名称 Digital clock recovery PLL
摘要 An apparatus comprising an analog circuit and a digital circuit. The analog circuit may be configured to generate a plurality of samples of an input signal in response to a plurality of phases of a reference clock. The digital circuit may be configured to generate an output signal and a clock signal in response to the plurality of samples and the plurality of phases. The clock signal is generally aligned with the output signal.
申请公布号 US7016447(B1) 申请公布日期 2006.03.21
申请号 US20010822041 申请日期 2001.03.30
申请人 LSI LOGIC CORPORATION 发明人 REUVENI DAVID R.
分类号 H04L7/00 主分类号 H04L7/00
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