| 摘要 |
A chip capacitor that includes a first and second terminal and a plurality of first and second conductive plates. The first terminal has a first interfacial attachment area that is adapted to be attached to a host substrate. The second terminal has a second interfacial attachment area also adapted to be attached to a host substrate. The first interfacial attachment area and the second interfacial attachment area separated by at least one relatively thin isolation strip such that the first and second interfacial attachment areas generally approach covering the entire attaching area of the chip capacitor. The plurality of first conductive plates are coupled to the first terminal and the plurality of second plates are coupled to the second terminal. In one embodiment, approximately 50% of the periphery of each first and second conductive plate is coupled to the respective first and second terminals.
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