| 摘要 |
<p>According to the convention dummy pattern generation method, a dummy pattern is generated by performing a complicated mask processing after completion of wiring. Accordingly, no timing calculation after the pattern generation is performed. In order to perform the timing calculation, it is necessary to consider the increase of the wiring capacity by the dummy pattern. However, feedback requires quite a time and it is difficult to cope with a timing error. There is provided a pattern generation method including steps of: generating a wiring pattern and a dummy patter in a wiring region of a semiconductor integrated circuit using an automatic arrangement/wiring tool, identifying wiring patterns and dummy patterns in the wiring region of the semiconductor integrated circuit, identifying a net having a difficult timing among the identified wiring patterns, identifying two dummy patterns adjacent to both side of the net having the difficult timing, and removing one of the dummy patterns adjacent to the both sides.</p> |
