| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a clock distribution circuit and a method therefor in a semiconductor logic circuit using a clock synchronization circuit, which is operated with reduced power consumption more effectively. <P>SOLUTION: A clock distribution circuit 10 generates gated clock signals 108 and 110 in clock generation circuits 20 and 22, in response to a clock enable signal 102. By supplying the signals to clock synchronization circuits 12, 14, and 16, 18, it becomes possible to reduce the power consumed by toggling the clock signals. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
