| 摘要 |
A method is described for fabricating a DRAM memory cell, which includes a trench capacitor and a select transistor. After the capacitor trench has been etched and optionally the first capacitor electrode has been produced, the trench is filled with a dummy filling. After the gate electrode and the first and second source/drain regions have been provided, the dummy filling is removed, and the capacitor dielectric and the second capacitor electrode are provided. As a result, it is possible to use temperature-sensitive materials for the capacitor dielectric and the second capacitor electrode despite the use of high-temperature steps. In the memory cell arrangement formed by this method, the direction of the conductive channel, which connects first and second source/drain regions to one another, can differ from the direction of the bit lines and of the word lines (e.g., by 45°).
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