发明名称 STACKED INTEGRATED CIRCUIT CASCADE SIGNALING SYSTEM AND METHOD
摘要 Integrated circuits (ICs) are stacked into modules that conserve PCB or other board surface area. The modules provide for lower capacitance memory signaling systems and methods for connecting stacked CSPs in a serial cascade arrangement. In one preferred embodiment, on-die terminations are used selectively to terminate a cascaded series of conductive paths. In another preferred embodiment, a form standard provides a physical form that allows many of the varying package sizes found in a broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design.
申请公布号 WO2006028693(A2) 申请公布日期 2006.03.16
申请号 WO2005US29867 申请日期 2005.08.23
申请人 STAKTEK GROUP L.P.;CADY, JAMES;RAPPORT, RUSSELL;WILDER, JAMES 发明人 CADY, JAMES;RAPPORT, RUSSELL;WILDER, JAMES
分类号 H01L23/02 主分类号 H01L23/02
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