| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a DLL (Delay Locked Loop) circuit including a means to prevent the state where the phase is locked erroneously. <P>SOLUTION: A course search circuit 17 is formed of flip-flops 17_1, 17_2 and an exclusive NOR 17_3. Lock point is roughly obtained through comparison between the reference clock CLKIN and feedback clock CLKFB. Next, amount of delay of a variable delay cell 16 is controlled with a control circuit 19 to set the phase between the reference clock CLKIN and feedback clock CLKFB to the predetermined phase by comparing the rising phase of the reference clock CLKIN with both rising and falling phases of the 1/2-divided feedback clock CLKFB2 with a fine search circuit 18 formed of the flip-flops 18_1, 18_2, 18_5, a switching circuit 18_3, and a delay circuit 18_4. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
