| 摘要 |
A method of designing a wiring structure of an LSI is capable of reducing a capacitance variation ratio DeltaC/C or a resistance-by-capacitance variation ratio Delta(RC)/(RC) of the wiring structure. The method sets a process-originated variation ratio (delta<SUB>P</SUB>) for the wiring structure, a tolerance (xi<SUB>C</SUB>) for the capacitance variation ratio (DeltaC/C), and a tolerance (xi<SUB>RC</SUB>) for the resistance-by-capacitance variation ratio (Delta(RC)/(RC)), evaluates a fringe capacitance ratio (F=C<SUB>F</SUB>/C<SUB>P</SUB>) according to a fringe capacitance C<SUB>F </SUB>and parallel-plate capacitance C<SUB>P </SUB>of the wiring structure, and determines the wiring structure so that the fringe capacitance ratio (F) may satisfy the followin
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