| 摘要 |
<P>PROBLEM TO BE SOLVED: To shorten the copying processing time of a plurality of pages while assuring the reliability of data. <P>SOLUTION: The memory system is equipped with a memory cell array 1, a bit line switch 4, first and second page buffers 2 and 3, a column switch 5, and an error correction circuit 11, and control circuits 7, and 10. Data exchange with the first page buffer is possible in the second page buffer. The control circuit performs the control to sequentially read out one or more pages from the (m) (m is a positive integer) page of the first block in the memory cell array up to the (n) (m<n) page for every page by controlling the bit line switch, and the first and second page buffers 2 and 3, and to perform error correction calculation in an error correction circuit by controlling the error correction circuit, and to perform writing to the second block in the erase state in the memory cell array, by controlling the first and second page buffers and the bit line switch. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
