Using oxynitride spacer to reduce parasitic capacitance in CMOS devices

摘要

A complementary metal oxide semiconductor (CMOS) device has a substrate 100 , a gate structure 108 disposed atop the substrate, and spacers 250 , deposited on opposite sides of the gate structure 108 to govern formation of deep source drain regions S, D in the substrate. Spacers 250 are formed of an oxynitride (SiO_xN_yC_z) wherein x and y are non-zero but z may be zero or greater; such oxynitride spacers reduce parasitic capacitance, thus improving device performance. A method of fabricating a portion of a complementary metal oxide semiconductor (CMOS) device involves providing a substrate 100 , forming a gate structure 108 over the substrate, depositing a first layer 104 atop the substrate on opposite sides of the gate structure to govern formation of deep source drain regions in the substrate, depositing an oxynitride (SiO_xN_yC_z) layer 250 atop the first layer (in which x and y are non-zero but z may be zero or greater), depositing a second layer 112 atop the oxynitride layer, and depositing a nitride layer 114 B atop the second layer.