发明名称 Frequency synthesizer using PLL architecture for wireless frequency allocation
摘要 An apparatus method to provide a frequency synthesizer using a phase locked loop in a communication device to provide a particular frequency allocation to generate an output from the PLL. The synthesizer includes a phase locked loop (PLL) circuit that has a feedback loop. The feedback loop has a feedback divider circuit that provides an N integer division of an output signal from the PLL in the feedback loop to close loop with the reference signal at a front end of the PLL. A value for feedback factor N to be used in the N integer division is based on a particular channel frequency selected and in which the feedback factor N is selected to provide a highest reference frequency available from the plurality of reference frequencies to generate the reference signal.
申请公布号 US2006057995(A1) 申请公布日期 2006.03.16
申请号 US20050060324 申请日期 2005.02.17
申请人 BROADCOM CORPORATION 发明人 CHIEN HUNG-MING
分类号 H04B7/00;H04B1/06 主分类号 H04B7/00
代理机构 代理人
主权项
地址