发明名称 |
Semiconductor memory device |
摘要 |
There is disclosed an NPN transistor comprising collector region of N conductivity type, base region of P conductivity type formed in the collector region, and emitter region of N conductivity type formed in the collector region. The collector and emitter regions define therebetween a planar PN junction. The NPN transistor further comprises a field plate electrode layer, when the transistor is viewed from above, extending from the periphery of the base region to the collector region. The field plate electrode layer comprises P conductivity semiconductor portion and N conductivity semiconductor portion. The P conductivity semiconductor portion is on the side of the base region. The N conductivity semiconductor portion is on the side of the collector region.
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申请公布号 |
US4707720(A) |
申请公布日期 |
1987.11.17 |
申请号 |
US19850802372 |
申请日期 |
1985.11.27 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
SHIRAI, KOJI;KAWAMURA, KEN |
分类号 |
H01L29/06;H01L29/40;H01L29/73;H01L29/78;(IPC1-7):H01L29/40;H01L29/04 |
主分类号 |
H01L29/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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