发明名称 Delay locked loop circuit, digital predistortion type transmitter using same, and wireless base station
摘要 Disclosed are a delay locked loop circuit capable of accurately extracting nonlinear distortion superimposed on an output of a digital predistortion type transmitter, the digital predistortion type transmitter, and a wireless base station using the same. The delay locked loop circuit comprises a variable delay element for receiving first input IQ signals Ir, Or, a subtractor for receiving signals Id, Qd based on output signals. If, Qf of the variable delay element, and second input IQ signals Ii, Qi, a delay comparator for receiving the output signals If, Qf of the variable delay element, and a smoothing filter for receiving and smoothing an output signal of the delay comparator, and outputting a smoothed signal to the variable delay element, in which delay control is implemented for checking distortion occurring to the output IQ signals due to the same passing through the analog circuit by means of the variable delay element. Either the first input IQ signals or the second input IQ signals are signals generated as a result of output IQ signals Io, Qo undergoing digital-to-analog conversion, and again undergoing analog-to-digital conversion after passing through an analog circuit. In particular, an IIR filter may be used for the variable delay element.
申请公布号 US2006056536(A1) 申请公布日期 2006.03.16
申请号 US20050030060 申请日期 2005.01.07
申请人 HORI KAZUYUKI;SUZUKI MAY 发明人 HORI KAZUYUKI;SUZUKI MAY
分类号 H04L25/03 主分类号 H04L25/03
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