| 摘要 |
PURPOSE:To improve the yield rate of products, by decreasing the number of times of a photoresist steps, which are for forming the source gate electrode and the source and drain regions of a CMOS integrated circuit from conventional three times to two times. CONSTITUTION:Photoresist layers 7d are formed on the surface of a polycrystalline silicon layer 5 corresponding to a region for forming a p-channel MOSFET and the gate-electrode forming part of an n-channel MOSFET. With the photoresist layers 7d as masks, the parts of the polycrystalline silicon layer 5 are formed. With the parts as masks, n-type diffused layers 8, which are to become the source and the drain of the n-channel MOSFET, are formed. Then, photoresist layers 7e are formed on the surface of the polycrystalline silicon layer 5 corresponding to the n-channel MOSFET region and the gate electrode forming part of the p-channel MOSFET. With the polycrystalline silicon layer 5 as a mask, the gate electrode of the p-channel MOSFET is formed, and p-type diffused layers 9, which are to become the source and the drain regions of the n-channel MOSFET are formed. Finally the photoresist layers 7e are removed. |
