| 摘要 |
PURPOSE:To facilitate the detection of a frame pattern and to shorten a synchronous return time by providing a serial/parallel converter, a channel replacing circuit, a residue calculating means, a phase difference calculating means, and a replacement control means. CONSTITUTION:Data sequecnces generated by multiplexing 64 sequences of low-order group output data by bits are sent as high-order group input data 101 and an expanding circuit 102 extracts at every 64 bits into 64 sequences. The respective sequences correspond to input lines of the channel replacing circuit 103. Dividers 1041-1043 read in a code of an 8-bit pattern for each frame in synchronism with a clock which is different only subframe phase in three-fold subframe cycles, and perform division between a code polynomial based upon the code as a coefficient and a predetermined generating polynomial to calculate the residue. A phase difference detector 105 finds the phase difference between codes from the residue calculation results of the respective dividers and uses the phase difference to perform channel replacement control over the circuit 103, which outputs information of 64 sequences. |
