| 摘要 |
PURPOSE:To greatly suppress the possibility of the pseudo synchronization of a data pattern by mistake by inserting two-phase frame pulses alternately into each frame additionally and detecting the two-phase frame pulse patterns alternately. CONSTITUTION:The two-phase pulses are signals 10 and 10', which are one frame out of phase with each other. A frame pulse F detecting circuit 31 detects the signal 10 in input data 1 and the signal is compared with a frame synchronizing pulse 11; when they do not match with each other, an error pulse (a) is outputted. The phase shift signal (e) between the signals 10 and 11 is outputted from an FF 55b. Similarly, when the signal 10' does not match with a frame synchronizing pulse 11', an error pulse (c) is outputted and an FF circuit (b) sends the pulse (a) and (c) as an error pulse signal 15 to a synchronism protecting circuit 4 to generate a step-out alarm signal 14, and sent to a phase shift signal or frame counter 40a through an FF circuit 59b from either of the signals (e) and (d) to thin out a clock by the shift (a), thereby attaining synchronization. |
