发明名称 VERTICAL DEFLECTION OUTPUT CIRCUIT
摘要 PURPOSE:To contrive to reduce the power consumption with simple circuit constitution by applying a prescribed power voltage to a push-pull circuit by the loss of a flyback pulse during the scanning period. CONSTITUTION:The charge/discharge capacitor C5 is kept to a voltage being nearly twice the power voltage by a flyback pulse voltage of a load circuit during the blanking period by a power voltage conversion circuit and the voltage is applied to a push-pull circuit to boost the flyback pulse voltage higher. Thus, the blanking period is reduced and the power voltage of the scanning period is decreased to reduce the heat loss of the transistors TR1, TR2 constituting the push-pull circuit. Moreover, the flyback pulse is lost during the scanning period to operate the transistors, the charge/discharge capacitor C5 keeps the power voltage, which is applied to the push-pull circuit to supply scanning current to the load circuit. Thus, the blanking period is reduced and the power consumption is decreased.
申请公布号 JPS6412682(A) 申请公布日期 1989.01.17
申请号 JP19870167872 申请日期 1987.07.07
申请人 NIPPON CHEMICON CORP 发明人 KAWAMURA KEIICHI
分类号 H04N3/16 主分类号 H04N3/16
代理机构 代理人
主权项
地址