| 摘要 |
<p>Disclosed is an interpolating circuit for producing an output signal having a delay time corresponding to a value obtained by performing interior division of a phase difference between entered first and second signals by a preset interior division ratio. The interpolating circuit includes a waveform synthesis unit and a bias control unit. The waveform synthesis unit includes an OR gate, which receives the first and second signals, for outputting the logic OR between these two signals; a first switch element inserted between a node, which is connected to an output terminal, and a first power supply and turned on and off by the output signal of the OR gate; a series circuit comprising a first constant-current source and a second switch element turned on and off by the first signal; and a series circuit comprising a second constant-current source and a third switch element turned on and off by the second signal; the series circuits being connected in parallel between the output node and a second power supply. On the basis of control signals that decide the interior division ratio, the bias control unit performs control in such a manner that current-path switches are turned on and off so that first and second current values, which are the totals of current values, will flow into the first and second constant-current sources, respectively.</p> |
