| 摘要 |
A frequency-divider circuit performs a division operation using a divisor that can include a fraction. In one such embodiment, a first divider module includes a divider circuit that operates to divide the frequency of an input clock signal and a phase-quadrature circuit. The first divider module generates a first-divider-output signal having periodic signals with regular phase displacement therebetween and a common period that is an integer multiple of the clock signal. Using this first-divider-output signal, a second divider module performs another divide operation and is clocked as a function of a delay effected by at least one of the periodic signals. The present invention is useful in a wide variety of applications including applications having a high frequency clock source that cannot tolerate excessive loading or jitter attributable to a divider circuit.
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