发明名称 |
Circuit for optimizing a delay line used to de-skew received data signals relative to a received clock signal |
摘要 |
Delay circuits have programmable delay elements to delay data signals so a clock samples the data signals in the middle of the eye window pattern. The clock is frequency divided by two, generating a divided clock coupled to a clock delay circuit and a data delay circuit generating a toggle clock and a delayed toggle clock that are sampled with the clock signal. A state machine varies the number N of delay elements selected in the data delay circuit until successive samples of the toggle clock and the delay toggle clock have opposite logic stages. The resulting number N is the number of delay elements required to generate a delay equal to one period of the clock. The delay of each delay element is adjusted using adjustment control signals until an N is generated that is within a predetermined range. The adjustment control signals are distributed to the data delay circuits.
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申请公布号 |
US7012956(B1) |
申请公布日期 |
2006.03.14 |
申请号 |
US20050055835 |
申请日期 |
2005.02.11 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
THOMSEN PETER M.;REESE ROBERT J.;SAENZ HECTOR |
分类号 |
H04B17/00 |
主分类号 |
H04B17/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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