发明名称 Pattern evaluation method, manufacturing method of semiconductor device, correction method of mask pattern and manufacturing method of exposure mask
摘要 A pattern evaluation method using a circuit arrangement provided with N (N is a natural number of 2 or greater) circuit groups having wiring whose widths are different to each other, each circuit group including first to Mth circuits having first to Mth (M is a natural number of 2 or greater) wiring formed of a conductive layer, respectively, each of the first to the Mth wiring having the same width that is electrically measurable, the pattern evaluation method includes: arranging patterns to be evaluated so that the Mth wiring or a layer in the vicinity thereof is locally removed; electrically calculating a first characteristic value indicating a characteristic of the first circuit including at least the wiring width of the first wiring; electrically calculating an Mth characteristic value which is a value indicating the characteristic of the Mth circuit and dependent on a geometric relationship between the pattern to be evaluated and the Mth wiring; and evaluating the characteristic of the pattern to be evaluated based on the first characteristic value to the Mth characteristic value obtained for at least two circuit groups of the N circuit groups.
申请公布号 US2006049838(A1) 申请公布日期 2006.03.09
申请号 US20050132397 申请日期 2005.05.19
申请人 KOBAYASHI YUJI 发明人 KOBAYASHI YUJI
分类号 G01B7/00;G01R27/08;G01B7/02;G03F1/84;G03F7/20;H01L21/027;H01L21/66 主分类号 G01B7/00
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