发明名称 Clamp limiter circuit with precise clamping level control
摘要 A limiter/clamp circuit is described having a sharp bend in the clamp characeristic and a transition from its linear range to its clamp range that occurs over a desirably small voltage range. The sharp bend is achieved by a feedback loop consisting of plural transistor elements configured in a current "mirror" feedback structure. This circuit is based on achieving an exponential/logarithmic dependence of the voltages and currents in the feedback loop, which serve to control the feedback signal to the base of a 2-transistor clamping device. The circuitry also provides relatively symmetric clamping.
申请公布号 US5119016(A) 申请公布日期 1992.06.02
申请号 US19910677212 申请日期 1991.03.29
申请人 AT&T BELL LABORATORIES 发明人 SEGER, ANDREW J.
分类号 G05F3/22;G05F3/30;H03K5/08 主分类号 G05F3/22
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